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Expert has microelectronics development, fabrication, manufacturing and intellectual property expertise acquired over a successful hands-on career spanning more than 3 decades, and covering CMOS semiconductor device technology nodes from 1um down to 14nm (current). His experience is both in-depth and broad-based, and includes Back-End-of-Line (BEOL) and Far-Back-End-of-Line (FBEOL) technology ownership of unit processes and process integration, as well as team leadership responsibility for Chip:Package Interaction (CPI, i.e. 'white bumps') and CPI integration for microelectronics packaging to meet highest-level industry standards for reliability and performance. His BEOL and FBEOL subject matter expertise pertains to advanced interconnect technology, etch technology (plasma, RIE, wet etch), polyimide material and process technology, process integration for both Al and Cu wiring BEOL structures, design groundrules, laser fuse technology, and FCPBGA via and packaging interconnects (solder bump, wirebond, Cu pillar structures, etc), and also includes aspects of flip-chip and 3-D packaging. He has long-term experience as a real-time problem solver in both the development and chip manufacturing environment, and in qualifying chip technologies to meet reliability constraints.

With 150 granted U.S. patents, he is recognized as an innovative intellectual property leader, and has been named an IBM Master Inventor. He is an author of 22 technical publications, to include journal papers and conference presentations and Proceedings. He has previously served 8 years as technical committee chair for the Symposium on Polymers for Microelectronics and has been a long-standing conference board member. Finally, Expert possesses exceptional communication, analytical, writing and interpersonal skills, as well as a strong work ethic, making him a highly desirable contact for consulting, technical support and expert witness services.

He has held multiple positions throughout his 32-year career in engineering, technology development, and manufacturing. He has assumed engineering responsibility for all aspects of process technology qualification for manufacturing (incl long-term ownership for plasma, RIE, polyimide, and final via sector processing), project management, real-time problem solving in time-sensitive development and manufacturing environments, process optimization, technology process integration, chip-package integration, and for structural aspects of wiring interconnects and CMOS design rules through 12 technology node generations from 1um (1985) to 14nm (2014). Expert spent many years as IBM Technical group leader for the CPI (Chip:Package integration) cross-functional team responsible for strategic technology development and implementation of reliable CPI configurations for advanced technology products for both Al and Cu-wired BEOL. Served as Intellectual Property (IP) Patent Review Board Chair for inventions in the area of FBEOL and CPI. He has developed and honed exceptional communication and interpersonal skills via his long-term role as technical team leader.

Currently providing technical consulting services to IC industry.