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Expert has more than 23 years experience in the semiconductor industry, much of this time in a technical management position at Intel. He has hands-on experience with nearly every facet of processing silicon wafers to manufacturing semiconductor devices. His strength is in his very broad, comprehensive understanding of the interrelationships between the various process steps (their tooling and materials) and the collective impact with regard to device technology and performance. Expert has contacts throughout the world that he can call on to answer a client question.

Expert has worked on numerous recent projects related to cost analysis and conceptual design of high-volume, $1 billion plus, front-end semiconductor manufacturing facilities (fabs) for US and international locations. He is familiar with what it takes to put one of these factories together, what it takes to operate it, and how much it costs to process a wafer. His knowledge also includes selection of equipment and layout of the cleanroom, including automation.


SEMICONDUCTOR TECHNOLOGY TRENDS ANALYSIS. He participates in analysis of long-term semiconductor technology trends. Historical analysis has shown that semiconductor device technology advances at regular intervals and with predictable capabilities. This trend enables reasonable projection and forecasting of device technology and associated manufacturing requirements for chips with 1000 times more functions than today that will be available in ten years. These projections allow him to determine which R&D efforts are needed now and what many of the requirements will be for future factories and manufacturing equipment.


SEMICONDUCTOR PROCESS FLOW DIAGRAMS. He can provide step-by-step process flow lists or diagrams for current and future device technologies (with representative cross-sections). These are generic, world representative "strawman recipes" for manufacturing various types of advanced integrated circuits. The diagrams provide a starting place for determining manufacturing requirements, listing manufacturing equipment needs, and determining costs. Process flows are available for DRAM, SRAM, FLASH, LOGIC (CPU) and SOC (System On a Chip). Process flows for future devices through the 64 gigabit DRAM technology equivalent are now available (year 2011 product introductions date).


Expert has experience working with attorneys and clients by providing technical information, insight, and expertise relating to patent, product, trade and standard practice issues.

Expert has been involved with inspection of bare wafers for cleanliness, impurities, defects, resistivity, thickness, flatness, size, and roughness. He is familiar with epitaxial silicon, buried layers, and silicon on insulator substrates (SOI). He has conducted ion implantation of isolation regions, threshold adjustment enhancement or depletion, source and drain regions, resist masking, through-layer implants, damage annealing, and dose monitoring. He has conducted wafer thickness reduction via sandblasting, backlapping, and backgrinding.


His knowledge includes thermal oxidation for isolation, gates, and nitridization in horizontal furnaces, vertical furnaces, and RTP chambers. He has worked extensively with chemical vapor deposition including APCVD, LPCVD, and PECVD dielectric films of oxide, doped glass and oxi-nitride for isolation, spacers, interlayer dielectrics, planarization, and passivation. He is knowledgeable of sputter and e-beam deposition of conductive films including polysilicon, aluminum, copper, tungsten, moly, titanium, chrome, and gold for gates, interconnects and via plugs, and bonding pads. He has worked with diffusion of boron, phosphorus, and arsenic dopants from gaseous, aqueous, solid and film sources for modification of semiconductor properties including junctions, thresholds, contact wells, gettering, and gas reflow. He is familiar with bulk and pattern etching of oxides, nitrides, silicon, and metals with wet chemicals (HF, nitric, phosphoric, KOH) and diode, triode, RIE, MIE, ECR, TCP, MORI, and Helicon plasma etching. He can answer questions on positive and negative photoresist spinning, exposure, and development as well as contact printing, scanning projection, step and repeat projection and step-and-scan pattern exposure.

He has worked on a wide variety of manufacturing automation topics, the majority of these in the semiconductor manufacturing environment. He has worked on small, single tool subsystems to complete factory design involving data automation, fixed function mechanization, and flexible robotic automation. Some of his projects include a robotic workcell automating wafer handling and equipment operation for nine process steps, robotic wetbenches for etching and cleaning, robotic transfer of wafers between plastic and quartz cassettes, and mechanized loading and unloading of furnaces with automated cantilever and soft-landing systems.

Other areas of his expertise include concept design, market surveys, and technology analysis on cluster tooling for semiconductor manufacturing. He has also written papers and reports on this subject.


Over the past nine years, Expert has been educating the public and promoting the use of products made primarily out of recycled plastics, including composites and straight HDPE. He has used 3-D CAD to model recycled plastic products. Some of these products include dimensional lumber shapes, landscape timbers, car stops, speed bumps, trash cans, fence posts and netting, park benches, picnic tables, and planters. His expertise includes design, fabrication, and applications of recycled plastic lumber.

Expert has used electrical, optical laser, and e-beam (SEM) microscopes and analysis tools for inspection and measurement of semiconductor film properties such as resistivity, impurity and defect levels, alignment, warp, bow, stress, threshold, breakthrough voltage, gain, and yield. He is familiar with parametric and functional testing of test structures and product devices for correlation to process parameters. He has conducted failure analysis including topographic location, micro-decoration, and strip-back to identify causes.

The majority of his current work is for suppliers of equipment to the semiconductor industry. He understands the technical and business aspects of both the semiconductor equipment user and supplier. He has conducted market surveys, technology projections and assessments, market modeling and projections, product evaluation, concept development, and system design. He has worked on cluster-tool process integration, PVD and CVD metal deposition, plasma etching, rapid thermal processing. planarization, and cleaning. Related topics include the entire range of vacuum integrated processing, chemical-mechanical planarization polishing, wet chemical cleaning, vapor cleaning and etching, low-damage plasma etching, ashing, and wetbenches.

Expert has worked with suppliers of materials for the semiconductor industry to help them better understand the industry's requirements. He explained to suppliers the need for specification requirements such as cleanliness, purity, flatness, and defect density. The materials he has worked with include chemicals, clean room surfaces, wafer contacting surfaces, fluid containment surfaces, masks, reticles, wafers, and wafer containers.