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Expert has spent most of his career in the semiconductor device and process technology areas. His experience is wide, with exposure to germanium and silicon discrete to large scale silicon integrated devices in the sub-micron regime. An area that is also of major interest to him is the optimization of process steps and integration, in order to achieve optimum device performance.

Expert has expertise in process modeling using supreme 4, and device modeling using Pisces 2b. His main emphasis has been on silicon devices for high voltage and high speed devices. Expert has modeled devices in the 0.55 micron length (CMOS). Expert has experience in total semiconductor processing including wafer cleaning, pre-treatments, oxidation, diffusion, implants, metallization, and passivation. He has worked with plasma and wet etching as well as photomasking.


Expert has been involved in developing process for isolation of devices. To do this, he has implemented different self-aligned technologies; under his guidance, the devices have low defect rates and low encroachment oxide isolation.

Expert has expertise in multi-level interconnect technologies; in fact, he was one of the early proponents of multi-level interconnect technology with planarization. He has experience in ARC, planarization via fill, and step coverage areas of interconnect technology, as well as SOG processing and contact issues.

Expert is experienced in silicon, oxide, nitride, and metal etch technologies for VLSI He also has background in applied material etchers, tegal etchers, drytek etchers, and lam etchers.

During his past employment, Expert has been responsible for the development of bipolar and biCMOS technology. He is well experienced in the device and integration problems of combining bipolar and CMOS. Expert has been awarded a number of patents in these fields.

This is one of Expert's strongest points. He has worked on improving FAB yield and final test yield of discrete devices to VLSI devices. He has excellent skills for identifying defects and causes of problems in this area, and solving them in the manufacturing environment.

Expert developed and patented an amorphous silicon diode for application with memory cells as load device. He also worked on deposition, doping, and passivation of amorphous silicon for vertical fuse technology.

Expert has had extensive experience in materials and characteristics of doped semiconductors. He has handled crystal growth and purification (float zone refining and doping) of germanium and silicon crystals. He has been involved in silicon material characterization for single crystal concentrator solar cell manufacturing.

Expert has extensive experience in different film depositions for peizoelectric crystal, capacitor, and semiconductor manufacturing. He has worked as a consultant to major equipment companies manufacturing deposition and etch equipment. He is familiar with microelectronic thin film applications.

Expert is knowledgeable of EEPROM and flash cells using electron tunneling phenomena in semiconductors. He has extensive background in the physics of tunneling.


Expert has been involved with manufacturing of semiconductors and electronic component products for over 20 years. He has expertise in equipment selection, optimization of layout, yield improvement, and manufacturability assessment.


Expert is knowledgeable of the technologies and devices currently used in medium and large scale semiconductor integration. He is familiar with the metal oxide semiconductor device form as the fundamental building block of both analog and digital circuits. He has been involved in characterization, modeling, manufacturing, and testing of these devices and circuits.


Expert has experience with integrated circuits and manufacturing from small scale to VLSI level. He has a wide range of experience in process integration to achieve the final results.


His experience in photovoltaics involves concentrator solar cell design, manufacturing, and testing. He worked primarily in concentration cell development for high-efficiency power generation.


Expert has done modeling work on TRAPATT and IMPAT diodes and microwave amplifiers. He also has some exposure to microwave ICs as a consultant.


Expert has experience in random access memory, including cell level, operation, manufacturing, and process. He has worked with bipolar, TTL and ECL memories, SRAM (MOS), DRAMS, and non-volatile memories.


He has been involved with memory cells using emitter coupled logic for high-speed bipolar and biMOS memory. He has patents in cell structures for ECL memories.


Expert has worked with bipolar junction transistors and Schottky and junction diodes. He has been involved in manufacturing, integration, and modeling of both standard bipolar and poly-emitter bipolar devices. He is also familiar with discrete high power and high voltage transistors and diodes.


Expert has worked on metal interconnection and dielectric planarization for interconnection. He has extensive knowledge of passivation methodologies. He has worked with barrier technologies for silicon interconnects.


Expert studied and implemented the use of various dielectric materials used in semiconductor manufacture and packaging as part of the IFI team investigating optimum interconnection and packaging issues.


Expert a background understanding of cell structures for non-volatile memories, problems of manufacture, reliability, testing, and yield issues in EPROM, EEPROM, and flash technologies. He developed a vertical fuse technology for metal to metal interconnection. He has extensive experience in manufacturing device technology and reliability testing of non-volatile devices.


As part of semiconductor technology and processing, Expert has been involved with optimization of doping processes using diffusion and implants. He has used rapid thermal processing.


He developed the EEPROM for IMP using their technology - proved the manufacturability and reliability.He was a consultant to EG & G - developed and implemented new high density technology for Infra red and optical sensors.He consulted for ITT, GA improving the breakage seen during process. He suggested handling and equipment modifications for brittle GAs wafers. He worked with Micro-Chip to eliminate the data loss due to process. He consulted on process development for EPRI/ Stanford concentrator Solar cell. He developed the first 26% efficiency cell.