Expert Details
IC Semiconductor, Solar Panel and Flat Panel Display Processing
ID: 723334
California, USA
Array
X-Ray flat Panel facilities designAdvise to market projection on various specialty chemicals and gasesConsult to specific wet processing device for flat panel operationValidation of high Bandgap junction design IPVerification of Intel case study in Fab operation
Education
Year | Degree | Subject | Institution |
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Year: 1979 | Degree: BS | Subject: Chemical Engineering | Institution: UC Berkeley |
Work History
Years | Employer | Title | Department |
---|---|---|---|
Years: 2007 to Present | Employer: Undisclosed | Title: Executive Technical Advisor | Department: US Design Center |
Responsibilities:Provides technical advise for solar panel start up establishing Design Center in US facility and Development facilities in Taiwan. |
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Years | Employer | Title | Department |
Years: 2007 to Present | Employer: Undisclosed | Title: Technical Consultant | Department: |
Responsibilities:Provides technical advice to MEMs design foundry working on Automobile sensor design and Medical devices. |
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Years | Employer | Title | Department |
Years: 2003 to 2007 | Employer: Engenuity System Inc. | Title: Executive Technical Advisor | Department: FPD Processing |
Responsibilities:Development of Engensys 5 and 7 productUS patent holder "Ground Grid enhancement for FPD plasma processing." |
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Years | Employer | Title | Department |
Years: 2001 to 2004 | Employer: Applied Materials Inc. | Title: Director of Engineering | Department: ETEC photo mask etch |
Responsibilities:Tetra II - photo mask etch, new product development |
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Years | Employer | Title | Department |
Years: 1990 to 2001 | Employer: Applied Materials Inc | Title: Director of New Product Development | Department: Advanced CVD metallization |
Responsibilities:Available upon request. |
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Years | Employer | Title | Department |
Years: 1988 to 1990 | Employer: Intel Corp | Title: Sr. Process Engineer | Department: EPROM TD |
Responsibilities:Interlayer Dielectric process development and qualification for 1M EPROM/ FLASH. |
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Years | Employer | Title | Department |
Years: 1983 to 1988 | Employer: Applied Materials Inc. | Title: Sr. Process Engineer | Department: Process Development |
Responsibilities:8300 and P5000 process development. |
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Years | Employer | Title | Department |
Years: 1980 to 1983 | Employer: Philip Moris Asia Inc | Title: System Engineer | Department: Engineering Serives |
Responsibilities:Responsible for China Joint Venture manufacturing operation. |
International Experience
Years | Country / Region | Summary |
---|---|---|
Years: 1980 to 1981 | Country / Region: China, PRC | Summary: Assigned to China Contract Manufacturing Operation |
Years: 1982 to 1983 | Country / Region: Manila, Philippines | Summary: Based in Philippines operation |
Years: 1990 to 2003 | Country / Region: Worldwide | Summary: While working for AMAT, responsible for various Joint Development Project with leading Semiconductor Manufacturing Fabs; including TI, Hitachi, TSMC, Charter, Siemens, ST. |
Years: 2006 to 2007 | Country / Region: South Korea | Summary: Conducted Joint Development with LCD fab and equipment qualification |
Years: 2007 to 2011 | Country / Region: China | Summary: Startup on Solar manufacturer in Joint Project for Solar Panel fabrication. |
Language Skills
Language | Proficiency |
---|---|
Chinese | |
Mandarin |
Fields of Expertise
chemical vapor deposition precursor material, metal organic chemical vapor deposition, rapid thermal semiconductor wafer processing, semiconductor integrated processing, semiconductor process gas, semiconductor processing equipment, semiconductor wafer etching, semiconductor wafer processing, chemical vapor deposition reactor, chlorine, engineering, etch pit density, etch pit density measurement, etch rate, four point probe, metallurgical engineering, nonreactive ion etching, semiconductor cluster-tooling processing, semiconductor wafer contact etching, semiconductor material processing, circuit integration