Expert Details

DRAM Design, Packaging, Modules, and Standards

ID: 727816 California, USA

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Expert has been a chairman of the JEDEC international standards organization since 1996, introducing then driving development of the DDR DRAM family of devices (DDR1, 2, 3, and 4). He has been chairman of the Timing, Small Modules, Packaging, and Socket committees. Expert's career highlights include 19 years with Intel, and also work with OCtel, S3, and Transmeta. More recently, Expert specialized in DRAM modules specification with Netlist, SimpleTech, and US Modular. Employer is Expert's consulting service, working with telecommunications and memory companies on training, product development, and analysis. Expert has numerous patents in ciruit design and packaging, and had performed expert witness consulting effort on multiple DRAM intellectual property cases. He is comfortable in front of crowds and speaks regularly at industry events.

Expert Witness for FTC case involving DRAM patents and royalties Expert Witness for court case involving DRAM patents and royaltiesMemory module design and standardization for packaging companySystems analysis and training for memory subsystems for telecommunications companyMemory training for memory company

Education

Year Degree Subject Institution
Year: 1988 Degree: None Subject: Computer Sciences Institution: Oregon Graduate Center, University of Portland, Stanford, Mission College

Work History

Years Employer Title Department
Years: 2001 to Present Employer: Undisclosed Title: Memory Technology Analyst Department:
Responsibilities:
Systems analysis, design, training for computer memory subsystems, focus on high density, low power, and requirements for servers and telecommunications.
Years Employer Title Department
Years: 2007 to 2007 Employer: US Modular Title: VP Engineering Department: Engineering
Responsibilities:
Manage specification and design of all custom products, work with sales and marketing to evangelize
Years Employer Title Department
Years: 2005 to 2007 Employer: SimpleTech Title: VP DRAM Technology Department: Engineering
Responsibilities:
Manage specification and design of all custom products, work with sales and marketing to evangelize
Years Employer Title Department
Years: 2002 to 2005 Employer: Netlist Title: Senior Memory Technology Analyst Department: Marketing
Responsibilities:
Manage specification and design of all custom products, work with sales and marketing to evangelize
Years Employer Title Department
Years: 1997 to 2002 Employer: Transmeta Title: Memory Technology Specialist Department: Engineering
Responsibilities:
Define and drive standardization of chosen memory technology
Years Employer Title Department
Years: 1995 to 1997 Employer: S3 Title: Graphics Architecture Specialist Department: Sales
Responsibilities:
Define and drive standardization of chosen memory technology
Years Employer Title Department
Years: 1974 to 2005 Employer: Intel Title: Field Applications Engineer Department: Sales
Responsibilities:
Support strategic accounts for all 20,000 Intel products
Years Employer Title Department
Years: 1988 to 1989 Employer: Octel Title: Diagnostic Engineer Department: Engineering
Responsibilities:
Write diagnostics and system bootstrap for voicemal system

Additional Experience

Expert Witness Experience
Expert witness for FTC case involving intellectual property usage and payment of royalties

Career Accomplishments

Associations / Societies
JEDEC
Awards / Recognition
Technical Recognition Award
Chairman's Award
Publications and Patents Summary
10 patents granted, 3 patent applications pending
4 published articles

Fields of Expertise

dynamic random access memory, extended memory, memory packaging, random-access memory, read-only memory

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