Expert Details
Computer Architecture, Memory System Performance, System Validation, Engineering Managemen
ID: 725609
Oregon, USA
Education
| Year | Degree | Subject | Institution |
|---|---|---|---|
| Year: 1989 | Degree: PhD | Subject: Computer Engineering | Institution: University of Kentucky |
| Year: 1978 | Degree: MS | Subject: EE | Institution: Indian Institute of Technology Bombay |
Work History
| Years | Employer | Title | Department |
|---|---|---|---|
| Years: 1998 to Present | Employer: Undisclosed | Title: Arch Manager | Department: Digital Enterprise Group |
Responsibilities:Driving microarchitecture of next generation Intel IA 32 CPUs |
|||
| Years | Employer | Title | Department |
| Years: 1995 to 1998 | Employer: DEC | Title: Principal Engineer | Department: Compiler Group |
Responsibilities:Drive compiler performance analysis for DEC C/C++ compliers on Alpha and other architectures |
|||
| Years | Employer | Title | Department |
| Years: 1990 to 1995 | Employer: Worcester Polytechnic Institute | Title: Assistant Professor | Department: Electrical and Computer Engineering |
Responsibilities:Available upon request. |
|||
Career Accomplishments
| Associations / Societies |
|---|
| Senior member of the IEEE; Eta Kappa Nu; Tau Beta Pi; Sigma Xi |
| Awards / Recognition |
|---|
| 7 Divisional Recognition Awards; Nehalem Architecture Team Department Award; Spontaneous Recognition Award |
| Publications and Patents Summary |
|---|
| 9 patent applications filed; 4 issued 25 refereed journal and conference publications |
Language Skills
| Language | Proficiency |
|---|---|
| HIndi | |
| Marathi |