Expert Details
Architecture and Strategy: Hyperscalers, ML and AI, DRAM/NAND Memory, CPU and Emerging Computing, IOT and Edge Computing
ID: 736149
Idaho, USA
Expert has three engineering degrees including a post graduate degree in electrical engineering from Columbia University. He is a senior memoir of IEEE and ACM. He has three published books on IOT and edge computing and several peer reviewed publishings.
Expert also has 47 patents in areas of imaging, DRAM and computer design, and advanced computing.
Education
| Year | Degree | Subject | Institution |
|---|---|---|---|
| Year: 2016 | Degree: Certificate Program (Currently enrolled) | Subject: Data Analytics and Deep Learning | Institution: University of Washington |
| Year: 2009 | Degree: Degree of Engineer (Doctoral) | Subject: Electrical Engineering | Institution: Columbia University |
| Year: 2001 | Degree: MS | Subject: Computer Engineering | Institution: National Technological University |
| Year: 1994 | Degree: BS | Subject: Computer Science | Institution: University of Wisconsin, Milwaukee |
Work History
| Years | Employer | Title | Department |
|---|---|---|---|
| Years: 2018 to Present | Employer: Undisclosed | Title: Director of Architecture | Department: Xbox and Azure |
Responsibilities:Accountability• Architect of hyper-scale Azure-based datacenter architecture to meet the needs of gaming, video streaming, and device interaction at global scale in 54 global data centers. • Develop an experience and silicon to system architecture to meet extreme low latency and high bandwidth needs of worldwide real-time datacenter driven entertainment. • Ensure pre-existing titles, game studios, developers are accounted for in cloud gaming system. Thought Leadership and Evangelism • Discover, adapt, and lead alternative use cases for Employer silicon in areas such as edge computing, hyperscale machine learning training hardware, serverless/FaaS computing farms, and edge computing devices. • Led initiative in advanced massively dense silicon architectures using immersion cooling. • Led disparate Employer teams and industry partners from ZT Systems, Mellanox, Nvidia, and AMD as a partnership. • Liaison and representative for Employer Surface, Xbox, and xCloud datacenter to JEDEC. • Lead new silicon designs at >10TF rendering capacity, advanced memory interfaces, and bleeding edge interconnects. |
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| Years | Employer | Title | Department |
| Years: 2018 to Present | Employer: Undisclosed | Title: Founder and CTO | Department: C-Suite |
Responsibilities:• Startup providing IoT solutions and services in areas of industrial automation, oil/gas analytics,and human tracking systems. • Provided solutions and guidance for deployments with McDonalds, Fleet Complete, ATT, and other Fortune 100 firms. • Developed strong industry partnerships with Dell (became primary IoT solutions provider), Digi, Eurotech, Toumetis, Cradlepoint and Coolfire |
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| Years | Employer | Title | Department |
| Years: 2017 to 2018 | Employer: Cradlepoint | Title: Director of Technology | Department: R&D |
Responsibilities:Strategist, evangelist and technical leader for Cradlepoint fog compute, SDN networking, and IoT solutions.C-Level Accountability • Technical council to C-Level staff. Reporting to CTO. • Developed the business case and technology for an IoT solution with growth of 30% YoY. • Fostered strong industry relationships: ATT, Verizon (5G LTE), Amazon, Employer, IBM, Ericsson, ARM, Bluetooth SIG, OpenFog Consortium, and HPE. Technical Management • Managed direct team of engineers from SaaS front-end to hardware edge development. Ownership of SOW and budget for contractual engineering services. • Architect and developer of new near range communications, AWS microservice based IoT management plane, mesh networks, and software-defined micro-segmentation of IoT devices in mass deployments with minimal supervision. • Senior technical staff to a multi-regional team of 160 engineers. Thought Leadership and Evangelism • Fortune 50 customer facing technologist. • Invited conference speaker and panelist. Provide thought leadership in whitepapers, books, CIO Magazine, and press interviews. • Director of intellectual property process, council, and protect growth for IPO candidacy |
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| Years | Employer | Title | Department |
| Years: 2015 to 2017 | Employer: Micron | Title: Director of Strategy and Distinguished Member of Technical Staff | Department: Compute and Network Business Unit |
Responsibilities:Advanced Computing and Memory GroupAccountability • Responsible for pathfinding, roadmaps, architectural definition, business development, design, and delivery of a game changing computing systems directly attacking Moore’s Law and Dennard Scaling through processing in memory (PIM) technology within a DRAM process. • Provided one on one customer guidance on real-world application of machine learning, inference engines, computer vision, imaging, and security with novel PIM architectures. • Senior technical council for Micron executive staff and technical lead for staff of 40. Technical Management • Managed direct staff of research engineers, computational scientists, and university interns. Managed budget of $500,000 for contractual engineering services and academic research. • Chartered with team construction and composition. Participated in the merger-acquisition integration of Convey Computers into group. Business Development • Development of new technologies, intellectual property, defensive publications, and creation of new markets for emerging computational memory. • Managed broad and complex technical partnerships across academia, software providers, silicon partners, and government agencies (Employer Research, Allen Institute for Artificial Intelligence, IBM, ARM, Nvidia, RIT, Intel, Sandia National Labs, NSA, National Geospatial Agency. |
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| Years | Employer | Title | Department |
| Years: 2004 to 2010 | Employer: Hewlett Packard Co. | Title: Master Architect of Technical Staff | Department: |
Responsibilities:Principal hardware/firmware architect for Embedded Systems Lab.Accountability • Responsible for all future digital imaging architectures including parallel ink arrays, dry electrophotographic devices, and capture systems. Responsible for 2.5M LOC and 25M gate SOCs. • Successfully deployed 37 independent product lines within a 6-year period ranging from small business imaging systems to enterprise/industrial copiers, printers, and network scanning. • Supervised architectural direction over imaging subsystems with a staff of 36 engineers. Technical Leadership • Institutionalized lab wide agile development methodologies and service orientated architecture principles. This effort resulted in a 2X reduction in defects and improved time to market by 50%. • Developed system wide process and schedules for new product turn-on from ASIC architecture and co-development through product launch which compressed ASIC turnon schedules by 75% with zero spins. • Researched and developed: CODEC acceleration through SIMD reinforcement, compiler optimization technology, voltage and frequency shifting code for efficient power usage for Energy Star certification, hardware acceleration for rendering, and inter-processor communication. |
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| Years | Employer | Title | Department |
| Years: 2000 to 2004 | Employer: Hewlett Packard Co. | Title: Engineering Scientist | Department: |
Responsibilities:Team Lead and Architect for Core Technology LaboratoriesAccountability • Development and turnon of HP’s first parallel inline laser system. Lead the design of: four plane parallel printing, high performance rendering, memory layout structures, and low-level code. • Led a team of six engineers in the delivery of initial board turn-on, new ASIC verification, schedules, requirements, and processor turn-on. • Responsible for LaserJet 4600, 5500, and 9500 product delivery |
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| Years | Employer | Title | Department |
| Years: 1995 to 2000 | Employer: Hewlett Packard Co. | Title: Firmware Engineer | Department: |
Responsibilities:Core Technology LaboratoryAccountability • Designed a system wide discrete event simulator to explore new architectural concepts. • Designed two early machine learning systems: a workload reduction tool to reduce the number of imaging tests from 20,000 to 50, a memory enhancement technology that trained HP LaserJet’s how to render polygons in real-time. • Directly responsible for the development of: novel image compression technologies, parallel algorithms processor analysis, and compiler efficiencies. • Technical lead for the EPFL university research program for 3 successful projects: DSP/MMX incorporation into the HP graphics engine layer, compiler improvements outside of assembly for MIPS processors, and display list optimizations. • Coordinated research work with HP Labs team in Palo Alto and Bristol. |
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| Years | Employer | Title | Department |
| Years: 1995 to 1995 | Employer: Hewlett Packard Co. | Title: Software Engineer | Department: |
Responsibilities:Boise Printer ResearchAccountability • Responsible for the delivery of the LaserJet 4j drivers. Software design and debug. • Developed a test strategy and test bed for confidence testing of the Windows drivers. • Worked with and mentored Chinese Academy of Science for contractual support of HP drivers |
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| Years | Employer | Title | Department |
| Years: 1974 to 1994 | Employer: Hewlett Packard | Title: Chief Architect - Distinguished Technologist | Department: Personal Systems Group and Imaging and Printing Business |
Responsibilities:Chief Architect of Embedded Systems – Imaging and Printing GroupAccountability • Technical council for executive staff and division vice president/general manager. • Accountable for over 40 cradle-to-grave product launches with over 30 million products shipped. • Responsible for ASIC, board level componentry, low level firmware and top of stack firmware with 22 development projects in flight. • Delivery of $130M in cost savings via ASIC super-integration and novel co-simulation tactics. Technical Management and Leadership • Strategist and lead for multi-discipline R&D lab comprising 500+ engineers and scientists for HP brand. Managed the Firmware Architecture Forum and Hardware Architecture Forum. • Direct manager of a senior team of 10 master architects involved in hardware and firmware design. Thought Leadership • Advanced HP’s strategic interests through architecting memory technologies, SOC architecture, HP TechCon, advancing HP Labs memristor storage applications and IP development. • Drove patentable innovation from research phase to products in ASICs, imaging, security, and power with Purdue, Rochester Institute of Technology, BSU, and Columbia University. • Research, design, prototyping, and evangelizing novel imaging, security, multi-touch and display technologies, and embedded technologies pervasive to HP. Corporate Partnerships • Developed strategic partnerships: ARM, Vivante, Employer, Intel, Marvell, and PMC-Sierra. |
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Career Accomplishments
| Associations / Societies |
|---|
| • Senior Member Institute of Electronic and Electrical Engineers, IEEE Computer Society • Senior Member Association of Computing Machinery • IEEE Technical Committee on Computer Architecture and Operating Systems • Chair and officer of Region 6 IEEE Computer Society: • Recipient of Outstanding Engineer Award for USA IEEE Region 6 (3 years) • ACM Distinguished Speaker |
| Professional Appointments |
|---|
| University Mentor • Mentored intern students – Stanford, Utah State, USC, Steven’s Institute, BSU |
| Awards / Recognition |
|---|
| HP Specific Mentions • HP TechCon “Let’s Make Some Silicon” Chair • HP Presidents Quality Award • Stanford Graduate School of Building Innovative Leadership Fellow |
| Publications and Patents Summary |
|---|
| Published Patents • 20 Issued: US and Worldwide • Notable: Apparatus and Method for In-Memory Operations • Notable: Aparatus and Method for Data Movement • Notable: Editin an Electronic Document • Notable: System for High Bandwidth Imaging Across Custom ASICs Pending Patents: 37 in process Corporate Publications: 11 Peer Reviewed Journals: 2 Book Publications :2 |
Additional Experience
| Training / Seminars |
|---|
| Industry and Academic Events, Seminars, Conferences and Publications • “Extreme Partitioning” IEEE Computer Society Region 6 Seminar 2006 • “A Case History of ARM Optimizations” ARM TechCon Invited Speaker 2014, Santa Clara, CA • “Computer Architectural Flops and Futures”, IEEE Region 6 Invited Keynote Speaker, May 2016 • “The Gateway Crisis of IoT”, Brightalk Webinar Series, June 2017 • “Edge Computing Efficacy”, IoT Evolution Las Vegas, July 2017 • “Value of Fog and Edge Computing”, CIO.com Magazine October 2017 • “Bluetooth 5 – One PAN to Serve Them All”, IoT Evolution Orlando, January 2018 • “The Internet of Things – From Hype to ROI”, Keynote for Idaho Business League, Feb. 2018 • “The 20% Rule – Data Generation versus Data Motion”, OpenFog World Congress, Oct. 2018 • “Computer Architectures for the 21st Century”, Keynote for Future Technology Conference Vancouver, BC, Nov. 2018 • “Machine Learning for the Rest of Us”, Idaho Technology Expo, Feb. 2019 |