Expert Details
Semiconductor IC Process and Operations Engineering, Bipolar & CMOS, Si & SiGe, RF, MEMS, Solar
ID: 723897
California, USA
Visited various foundries world wide and brought up, co-developed or transferred mixed-signal and analog process Bipolar, CMOS and BiCMOS technologies. Also negotiated wafer prices, secured wafer supply capacity, and held periodic technical review meetings. Lined up and selected strategic fab/technology partners for future products requirements. Formed strategic partnerships for total manufacturing and joint sale on selected products.
Education
| Year | Degree | Subject | Institution |
|---|---|---|---|
| Year: 1971 | Degree: BS | Subject: Physics | Institution: St. Xavier's College, Gujarat Univ |
| Year: 1973 | Degree: MS | Subject: Physics | Institution: Gujarat University |
| Year: 1977 | Degree: MS | Subject: Electrical Engineering | Institution: Univ. of Cincinnati, OH |
Work History
| Years | Employer | Title | Department |
|---|---|---|---|
| Years: 2005 to Present | Employer: Undisclosed | Title: Consulting, V P of Operations | Department: Undisclosed |
Responsibilities:One of the two key executives. Helped start the company.Company is designing very advanced RF IC's using Si, Si-Ge and GaAs based processes. Establish new foundry relationships with targeted foundries with Si and SiGe technologies meeting RF IC product needs. Help prepare V C presentations and participate in the meetings. Visit potential customers, vendors, fab/technology suppliers to form strategic partner relationships. Help prepare Sales presentations and other sales material. |
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| Years | Employer | Title | Department |
| Years: 1989 to 2005 | Employer: Undisclosed | Title: Sr. Director | Department: Undisclosed |
Responsibilities:Available upon request. |
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| Years | Employer | Title | Department |
| Years: 1986 to 1989 | Employer: Philips/Signetics | Title: Undisclosed | Department: Technology Development/Fab 16 |
Responsibilities:Managed two engg groups for advanced products and technology development Fab: Bipolar, CMOS, BiCMOS. Diffusion, Oxidation, Anneal & Thin Films process engineering groups. Also, managed Electrical Test and Yield Enhancement engineering group. |
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| Years | Employer | Title | Department |
| Years: 1980 to 1986 | Employer: Undisclosed | Title: Section Manager | Department: Undisclosed |
Responsibilities:Fab 6 Process Engg Section Head: CMOS. BiCMOS for advanced DRAM's, SRAM's and micro-processors chips. Set-up and started half of the fab, managed all white-room ( diffusion, oxidations, anneals, very thin gate oxides, Implants, Thin-films ( ACVD, PCVD, PELPCVD, LPCVD) process engineering groups. Introduced megasonic cleans, low stress PELPCVD processes, very thin gate oxides.Technology Development Group: Bipolar & BiCMOS for PROM and PAL products. Co-authored one patent on Pt-Si fuse formation using novel processing technique. |
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| Years | Employer | Title | Department |
| Years: 1978 to 1980 | Employer: Undisclosed | Title: Sr. Process engr | Department: Undisclosed |
Responsibilities:Available upon request. |
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| Years | Employer | Title | Department |
| Years: 1977 to 1978 | Employer: Univ. of Cincinnati | Title: Undisclosed | Department: ECE Dept |
Responsibilities:Set-up Epitaxial reactor. |
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| Years | Employer | Title | Department |
| Years: 1977 to 1977 | Employer: Rensselaer Polytechnic Institute | Title: Undisclosed | Department: ECE Dept |
Responsibilities:Available upon request. |
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| Years | Employer | Title | Department |
| Years: 1974 to 1976 | Employer: Undisclosed | Title: Research Assistant | Department: Undisclosed |
Responsibilities:Available upon request. |
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International Experience
| Years | Country / Region | Summary |
|---|---|---|
| Years: 1989 to 2005 | Country / Region: Japan, Korea, Singapore, Taiwan, Malaysia | Summary: Visited wafer foundries and other suppliers: 1. To bring-up, co-develop or transfer mixed-signal and analog process Bipolar, CMOS and BiCMOS technologies. 2. To negotiate wafer prices, secure wafer supply capacity, and hold periodic technical review meetings. 3. To line-up and select strategic fab/technology partners for future products requirements. 4. To form strategic partnerships for total manufacturing and joint sale on selected products. |
| Years: to Present | Country / Region: Germany, Austria | Summary: Visited wafer foundries: 1. To bring-up, co-develop or transfer mixed-signal and analog process Bipolar, CMOS and BiCMOS technologies. 2. To negotiate wafer prices, secure wafer supply capacity, and hold periodic technical review meetings. 3. To line-up and select strategic fab/technology partners for future products requirements. |
| Years: 2005 to Present | Country / Region: India | Summary: Visit to train RF design engineers in selected aspects of manufacturing to shape/improve their view on designing for better yield/cost. |
Career Accomplishments
| Associations / Societies |
|---|
| Member of FSA's Tech Sub-Cmt. IEEE Member. |
| Publications and Patents Summary |
|---|
| One patent on Pt-Si formation. One paper & thesis published on TCE Gettered MOS gate oxide and its impact on improving gate leakage current. |
Additional Experience
| Training / Seminars |
|---|
| For internal company use only at previous companies: Developed short courses and trained product engineers on basic yield improvement methods using SPC(Statistical Process Control). Developed a seminar and trained design engineers for design for manufacturability. Trained engineers at foundries on use of basics of SPC and implementing them. Trained engineers at foundries on details of specific fab process steps developments or improvements during technology transfer. |
| Vendor Selection |
|---|
| In Mixed Signal Analog and RF areas, strategized foundry, assembly and test vendor selection and established long term relationships. |
Language Skills
| Language | Proficiency |
|---|---|
| Hindi | |
| Gujarati | 1st language. |
Fields of Expertise
doping agent, drive diffusion, integrated-circuit manufacturing, manufacturing, microelectronic device manufacturing, operational auditing, operations management, predeposition diffusion, production process, semiconductor diffusion, semiconductor dopant lateral diffusion, semiconductor doping, semiconductor material manufacturing, semiconductor wafer processing, operational process improvement, operations engineering, operational testing, planarization, photochemical etching, semiconductor device testing, four point probe, semiconductor device physics, device physics, semiconductor economics, plant operations management, epitaxial silicon, semiconductor inversion layer, semiconductor integrated processing, semiconductor fabrication clean-room management, semiconductor material characterization, semiconductor device manufacturing, metal-oxide semiconductor material, semiconductor ion implantation, semiconductor material, semiconductor device, production control, epitaxial reactor