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Expert owned the copper plating process module at Intel's Assembly Test Technology Development site for ~2 years, focusing on plating deposition process, plating solution chemistry, plating equipment and thickness uniformity control as pertaining to IC substrate manufacturing. He interfaced with plating solution and equipment suppliers, as well as substrate manufacturers, to push the state of the art for both electroless and electrolytic copper plating. His work involved selection and implementation of new unfilled and filled via plating chemstries, periodic reverse pulse plating equipment, jet plating equipment, and continuous plating equipment for panel-level plating. His work also included periodic troubleshooting of high volume manufacturing lines to resolve electrolytic plating issues, which included bubble entrapment, via delamination, and large dimple formation, as well as electroless plating issues such as incomplete via coverage, thickness non-uniformity across the panel, and foreign material induced quality issues.

He provided consulting expertise to a company building MEMS-type devices consisting of a sequential build process which suffered from a corrosion issue. Provided a detailed review of potential sources of corrosion, and proposed a corrective action plan to address the issues.