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Mr. Christopher Expert has expertise in systems architecture and hardware design in advanced signal processing and multiprocessor systems, and has spent significant time in the analysis and synthesis of video and audio compression systems. He consults on hardware architectures for communication processors, tree machines for speech recognition and parallel processing applications, processor design, bus architectures, and ASIC applications. His experience includes design of a reconfigurable systolic/tree multiprocessor architecture, a 3 Gigaflop/sec VME-based multiprocessor design; architecture and design of a 20 GBit/sec central switch network for signal processing; and hardware designs of VSB/QAM/CPM high bandwidth communication links (both transmission and reception). His experience also includes custom CMOS ASIC design and a microprocessor-based peripheral power sequencing control systems. Expert is well-versed in the analysis of signal processing benchmarks and statistical communication channel performance, reduced instruction set computing (RISC), digital and acoustic signal processing, airborne hardware systems, Unix shell programming and O/S utilities, DOS, Basic, Fortran, and C.

A large portion of Expert's consulting involves the definition and synthesis of multi-processor architectures for general data and signal processing. His work has a particular emphasis on processor design and communications networking.


For the last four years, a significant portion of Expert's work centered around the design and testing of high-definition television (HDTV) and digital NTSC TV (DTV) systems. This focus is primarily upon hardware design and algorithm synthesis. He has also been involved with the synthesis of vector-quantized-based stereo audio encoders/decoders. Advanced wavelet-based audio and video compression work is currently in the design and analysis stages of development.


Expert has done both hardware and software design for a variety of acoustic signal processing tasks including a 64-sub-band high-fidelity adaptive acho canceller consisting of fixed-point and floating-point dsp's and shared memory. He has also written many "core" signal processing routines such as FIR, IIR, and adaptive LMS filters.

Expert has designed various uni- and multi-processor systems for general purpose scientific processing and signal processing. Particular attention was given to efficient communication networking and various architecture topologies such as multi-hop rings, 2-D mesh, and linear systolic arrays.